Layout Design of Level Triggered Delay Register using 90 nm Technology
نویسندگان
چکیده
منابع مشابه
Ultrafast CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology - Electronics Letters
Introduction: The increase of transistor speed in CMOS technologies has been reached mainly by scaling the gate length of the MOS transistors. For the most advanced technologies, gate lengths down to 40 nm with an ft of 243 GHz [1] have been reported. This allows performances comparable to expensive III-V technologies based on GaAs or InP and in addition the potential for very large scale integ...
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ژورنال
عنوان ژورنال: International Journal of Computer Applications
سال: 2015
ISSN: 0975-8887
DOI: 10.5120/21783-5060